An ECL RISC multiprocessor
Brett Foster, Cedell A. Alexander, A. Roberts, David Roberts · 2002
The authors describe how an upgrade to the MIPS R6000 ECL chip set, the R6000A CPU and the R6020A SBC, implements a sophisticated coherent cache protocol to support multiple processor systems, and how software uses the system. Particular attention is given to the cache subsystem, the cache control attributes, the cache line states, and the software environment.>