Special hardware for computing the probability of undetected error for certain binary CRC codes and test results
D. Chun, Jack K. Wolf · IEEE Transactions on Communications · 1994
A hardware device for efficiently evaluating the probability of undetected error for a class of CRC error detection codes with a large number of parity check digits is described. The generator polynomial for the codes in this class are of the form g(x)=(1+x)p(x) where p(x) is a primitive irreducible polynomial. The degree of g(x), R, is the number of parity check digits. Using this hardware, a search was conducted for codes in this class (for 8/spl les/R/spl les/39) which are "proper" for shortened block lengths. A table of codes satisfying this condition is included.>