ACCORD : Automatic Catching and Correction of Logic Design Errors in Combinational Circuits
Pi-Yu Chung, Ibrahim N. Hajj · 2005
Thas paper descrabes an approach io iletectzng aiid correctang desagn errors an conibanatzonal gnie-lewl czrcuat descraptaon an the process of verafyaiig a desagn an terms of ats functzonal speczficataon A coinplete set of Sangle-Logac- Desagn-ErrorjSLDE) models are suggested and a new classtjicaizori by carrecinbilii y as gaven. A determznastzc algoraihni zs pioposed to COTrect these errors. Our algorzthna as robiisf zii ihe seiise that af an erroneous czrcuzt can satzsfy ihe S‘LDE models, a solutzon as guaranteed. The correctroil of miilfipie logac desagn errors zs also dzsciissed