A FPGA architecture for real-time processing of variable-length FFTS
Stefan Langemeyer, P. Pirsch, Holger Blume · 2011
A new FFT architecture for real-time implementation of large FFTs is presented. The architecture supports both, high throughput and variable-length processing capabilities. The implementation is configurable at run-time, in order to compute power-of-two length ranging from 16 to 2n. It supports efficient integration of data scaling techniques. A radix-23DIT FFT algorithm is derived, which minimizes the number of multipliers and supports simple reordering.