A 50 Mip Atm Cell Processor for B-ISDN
J.J. Hickey · 1992
Each instruction has conditional evaluation 6. Memory operations are asynchronous. Wc tlcscribe an cxperiniental Reduced Instruction Set Computer (RISC) for Asynchronous Transfer Mode (ATM) cclls. The chip uses a. lpni process a.id iiitegrates sev- era1 network interfaces and thc specialized RISC processor. System Overview I'liis experimental researcli prototypr device can he used for the' ccll intdacc for many Rroadbaiid 1iitrgra.ted Services Digital Ketl\rorli (KISDK) components, including policing ;ind admission control uiiit,sj statistical multiplexors; and hcatler proccssors. Nctwor1.c data rates up to 622;\11jil/sec caii be achieved, ~vi~li an instruction processing rate of' ,50l\I I I z.