Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip
Robert Molyneaux, Tom Ziaja, Hong Bin Kim, Shahryar Aryani, Sungbae Hwang, Alex Hsieh · 2007
The Niagara2 System-on-Chip is SUN Microsystem’s latest processor in the Eco-sensitive CoolThreads line of multi-threaded servers. This DFT survey of the Niagara2 chip introduces the RAWWCas memory test, a Hybrid Flop Design and a fast efficient bitmapping architecture called DMO. It also showcases some excellent DFT results for this challenging system- on-chip design project.