Skein Tree Hashing on FPGA
Aric Schorr, Marcin Łukowiak · 2010
This paper focuses on design and analysis of a Field Programmable Gate Array (FPGA) hardware for Skein's tree hashing mode. Several approaches on how to modify sequential hashing cores, and create scalable control logic in order to provide for high-speed parallel hashing hardware are presented and analyzed. The results are compared to the current sequential designs of Skein, providing a complete analysis of the performance of Skein in custom FPGA hardware. The post place-and-route results show that our tree based Skein-256 design achieved a throughput of 3 Gbps using two cores, and 5.6 Gbps for four cores as compared to 1.6 Gbps for sequential systems. The design is parametrizable using leaf-size (YL), nodefanout (YF), and internal block size (ISBIT). The control logic follows the same methodology, but is designed for a specific number of cores (NCORE) to correctly handle the core assignment strategy and control.