On the determination of threshold voltages for CMOS gates to facilitate test pattern generation and fault simulation
Kuen-Jong Lee, Jing-Jou Tang, Wern-Yih Duh · 2002
An accurate threshold voltage determination method for CMOS gates is presented that can be used to enhance the performance of test pattern generation (TPG) and fault simulation (FS). By using this model the "Byzantine General" problem during the FS and TPG can be overcome. Experimental data show that SPICE like accuracy can be achieved without carrying out circuit-level simulation.