MAX II: A low-cost, high-performance LUT-based CPLD
Paul Leventis, Brad Vest, Mike Hutton, David M. Lewis · 2004
This paper describes the MAX II CPLD architecture. Departing from traditional CPLD product-term logic elements and global routing, it instead employs FPGA-like look-up tables and channel-based routing. It integrates a flash memory for configuration and a voltage regulator for core power flexibility, and delivers 2.9/spl times/ higher logic density, 2.2/spl times/ greater performance, and consumes >15/spl times/ less power in 1/6 the die size of its predecessor, the MAX 7000A.