Scalable Performance Scheduling for Hardware-Software Cosynthesis
Thomas Benner, Rolf Ernst, Achim Österling · 1995
The paper presents a static process scheduling approach as a front-end to hardware-software cosynthesis of small embedded systems which allows global system optimization. Unlike earlier approaches, scheduling is executed before hardware definition assuming scalable system performance. Scheduling supports process communication and external timing requirements. We explain the algorithm and give results using an example. 1 Introduction Process scheduling is a well known problem in embedded system design. In current approaches, the hardware-software architecture is widely known at compile time. With the advent of hardware-software co-synthesis, hardware-software partitioning can be moved to a very late design stage (late binding) because changing system descriptions and generating and modifying hardwaresoftware architectures has become much easier. This is very much like the automation of physical layout has reduced the cost of netlist changes and logic synthesis has simplified RT-level ...