Power/performance advantages of victim buffer in high-performance processors
Gianluca Albera, Ruth Iris Bahar · 1999
In this paper, we propose several different data cache configurations and analyze their power as well as performance implications on the processor. Unlike most existing works in low power microprocessor design, we explore a high performance processor with the latest innovations for performance. Using a detailed, architectural-level simulator, we evaluate full system performance using several different power/performance sensitive cache configurations. We then use the information obtained from the simulator to calculate the energy consumption of the memory hierarchy of the system. We show that victim buffer offers improved cache energy consumption over other techniques (10% compared to 3.8%), while at the same time providing comparable performance gains (3.54% compared to 3.45%).