Multiplierless multirate decimator/interpolator module generator
Shyh-Jye Jerry Jou, Kai-Yuan Jheng, Hsiao‐Yun Chen, An-Yeu Andy Wu · Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits · 2004
A module generator, which can automate the process of designing high-speed low-complexity multistage multirate decimator/interpolator, is presented. The generator exploit architectural symmetries in linear phase filters and multistage multirate interpolated FIR filter design methodology for low complexity. In addition, the polyphase representation is used to decompose the filter into subfilters. The resulting filters utilize canonic signed digit (CSD) multipliers, a transposed direct form structure, and carry-save addition for high speed. A filter design example with TSMC 0.25 /spl mu/m standard cell for 64-QAM baseband demodulator shows that the area is reduced by 39% for low-complexity applications. Moreover, for high-speed application, the chip can operate at 714MHz. Finally, a designed decimator which is used in the CDMA cellular shows that the area is reduced by 70% as compared with conventional approach.