An embedded stack microprocessor for SDH telecommunication applications
M. Stadler, M. Thalmann, T. Rower, N. Felber, Wolf Fïchtner · 2002
In this paper we present an application-specific microprocessor core with a stack architecture optimized for use in broadband telecommunication ASICs. The microprocessor was integrated in an application on the same die as the complete data path of an SDH add-drop multiplexer (ADM). It handles over 1 million interrupts per second from 29 asynchronous sources. Due to this high interrupt rate extremely efficient context switching is required: only two extra cycles per interrupt call. The top four stack elements are directly accessable as registers and ALU instructions are computed in parallel with push or pop commands. An independent ALU for address processing enables compact and very efficient code generation. A prototype ASIC has been implemented in 0.8 /spl mu/m CMOS technology.