A video buffer controller design for HDTV/BISDN system
Shyi-Ching Liau · 2002
Represents the design of a video buffer controller for an HDTV/BISDN experimental research prototype which demonstrates digital HDTV coding and transport at STS-3c rate within an ATM payload of 130 Mb/s. With a generic design, this video buffer controller would be suitable both for the transmitting end and the receiving end. A nibble-wide quaternary data processing algorithm is introduced to make it possible for the system to interface with commercial memory available today to accommodate with a high data rate processing. Some other functions, such as calculation and reporting of buffer occupancy, address jumping and alarm flag generation, are also provided.>