A Low-Power Synchronizer for Multistandard Wireless Communications
Tsung‐Heng Tsai, Yi‐Jen Chen, Chi-Fang Li, Guo-Hua Pu, Yuan‐Sun Chu · IEEE Transactions on Circuits & Systems II Express Briefs · 2008
This paper proposes a low-power ASIC design of pseudonoise code synchronization for wireless code-division multiple access (WCDMA), CDMA2000, and IEEE 802.11 g systems. WCDMA and CDMA 2000 are two major standards in third-generation (3G) communication systems. Since 3G and 802.11 g are based on the same CDMA technology, there are common parts in the code synchronization hardware. We integrate the three systems on one ASIC. In addition, we use three kinds of low-power techniques in the design that include power management, absolute weighted magnitude calculation, and spurious power suppression adder. They can save 57.37% power consumption in WCDMA synchronization, 6.06% power consumption in CDMA2000 synchronization, and 84.69% power consumption in 802.11 g synchronization. The low-power synchronizer is implemented with an operating voltage of 1.2 V, 0.13-mum CMOS technology, and chip area of 2.1times 2.1 mm2.