A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture
Claudio Mucci, Fabio Campi, Antonio Deledda, Andrea Fazzi, Maura Ferri, M. Bocchi · 2005
Reconfigurable processor architectures (RAs) have been proving as an effective way to couple significant performance improvements with severe energy constraints, such as those imposed by modern portable real-time applications. XiRisc is a VLIW RISC processor architecture featuring a reconfigurable dataflow-oriented functional unit, the so-called PiCoGA, allowing run-time dynamic extension of the instruction set. In this paper, we propose a LISA-based instruction set simulator (ISS) for the reconfigurable processor, retargetable through a dynamically linked library that emulates instruction set extension. The ISS comprises a SystemC system-level model with embedded bus architecture and memory hierarchy (on-chip and off-chip) to provide a reconfigurable system-on-chip performance evaluator.