An automatic test pattern generation program for large ASICs
D.L. Liu, Rajesh Galivanche, Chi-Chun Hsu · 2003
An automatic test pattern generation program (ATPG) is described for large, application-specific integrated circuits (ASICs) designed with a scan path technique. This program was implemented with an improved deterministic test generation algorithm that makes use of a split model for circuit representation and multiple testability heuristics for efficient search. The program can also interface to a hardware accelerator to speed up the test compaction process.>