Pipelined TSPC barrel shifter with scan test facilities for VLSI implementation of high speed DSP applications
R. Pereira, Juan A. Michell, Jose M. Solana · 2003
A barrel shifter for high speed data processing is described, together with the test-oriented structure which it has been provided with. The circuit has a pipeline architecture and has been designed using the TSPC strategy, which has allowed the achievement of a high operation rate. Its implementation has been carried out in full-custom style with 1.5 mu m CMOS technology. The incorporated test-oriented structure allows serial acquisition of output data using the normal mode instruction register.>