A Cost/Error computing circuit for HDTV coding
Pierre Penard, P-R Rogel, J-L Sicre · European Solid-State Circuits Conference · 1991
The proposed circuit computes the difference between two rectangular blocks of pixels at a maximum rate of 54 MHz. It has been designed by using rapid prototyping methods that involve both high-level behavioural language for architecture implementation and standard-cells and layout generators for layout design. The core of the circuit is a programmable delay line of 432×32 bits length implemented on 6.75 mm2 in a 1 micron Cmos tecnology, the total chip area is 30 mm2. The circuit is planned to be widely used in the second High Definition Television (HDTV) coder developed by THOMSON to provide MAC compatible HDTV signals for the 1992 Olympic Games.