A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition
Yuichiro Murachi, Yusuke Fukuyama, R. YAMAMOTO, Junichi Miyakoshi, Hiroshi Kawaguchi, H. ISHIHARA, M. Miyama, Yoshio Matsuda, Masahiko Yoshimoto · IEICE Transactions on Electronics · 2008
This paper describes an optical-flow processor core for real-time video recognition. The processor is based on the Pyramidal Lucas and Kanade (PLK) algorithm. It features a smaller chip area, higher pixel rate, and higher accuracy than conventional optical-flow processors. Introduction of search range limitation and the Carman filter to the original PLK algorithm improve the optical-flow accuracy, and reduce the processor hardware cost. Furthermore, window interleaving and window overlap methods reduces the necessary clock frequency of the processor by 70%, allowing low-power characteristics. We first verified the PLK algorithm and architecture with a proto-typed FPGA implementation. Then, we designed a VLSI processor that can handle a VGA 30-fps image sequence at a clock frequency of 332MHz. The core size and power consumption are estimated at 3.50×3.00mm2 and 600mW, respectively, in a 90-nm process technology.