Array processors for DSP: implementation considerations
Matej Zajc, R. Sernec, Jurij Franc Tasič · 2005
Modern DSP applications depend on high throughput and massive data used in computations. Array processors present an appealing approach of parallelism exploitation for meeting real-time requirements. The intention of the paper is to address the potential of a fixed interconnection topology systolic array as well as alternative implementation approaches for reconfigurable topology systolic arrays. Our work is merely limited to array processors that work in a so-called systolic manner.