Utilizing synthesis to verify Boolean function models
Azam Beg, P. W. C. Prasad, Walid Ibrahim, Emad Abu Shama · 2008
In this paper, we compare two different Boolean function reduction methods in order to justify the analytical model of the Monte Carlo data for Boolean function complexity. We use a binary decision diagram (BDD) complexity model (proposed earlier) and weigh it against the complexity behavior generated by Synopsys Design Compiler (DC). We use this synthesis tool (that utilizes a standard cell library) to generate RTL hardware description of Monte Carlo circuits as gate-level netlists. The two reduction methods (model and DC) transform an arbitrary function into a much-reduced representation of the same function. The comparison confirms that the behavior of Boolean function complexity using the model and the DC is visually and statistically similar; the similarity holds true for BDDs representing functions comprising a wide range of variables and minterms.