On-chip memory module designs for video-signal processing
Tian‐Sheuan Chang, Chein-Wei Jen · IEE Proceedings - Circuits Devices and Systems · 1997
Two embedded memory designs are proposed for video-signal processing. Concurrent line access performs multiple-port memory accesses at the hardware cost and access time of a single port. It uses 62.24% of the area required by a conventional dual-port memory and is only 7.6% larger than a single-port 2 K × 8 memory. The block-access mode combines address decoders and generators, yielding block-access mode times 26% faster than conventional schemes for a 256 words × 32 bits memory size. Despite some preferred-access-order restrictions, the designs incur no loss of generality because video algorithms possess high data parallelism and low dependence.