A gate-array-based 666 MHz VLSI test system
S. Kikuchi, Y. Hayashi, Takashi Suga, J. Saitou, M. Kaneko, Takaaki Matsumoto, R. Yoshino · 2002
A 666 MHz VLSI test system with a dedicated memory test pattern generator was developed. A loose-timing data transfer scheme was employed for better integration of a shared-resource unit into the per-pin tester-architecture, Timing control resolution of 12.5 ps was achieved within a normal framework of a gate array LSI. A simple and low-cost timing calibration-technique was developed to offer accurate test timings. Parallel operation of the memory test pattern generators was used to realize a non-interrupted pattern generation at the maximum speed.