A system for fault diagnosis and simulation of VHDL descriptions
Vijay Pitchumani, P. Mayor, N. Radia · 1991
This paper describes a compiler and algorithms for simulation and fault diagnosis of computer hardware modeled in VHSIC Hardware Description Language(VHDL).Given a VHDL description, the compiler creates an internal representation.For simulation, a discrete-event based compiled code simulation algorithm is used.For fault diagnosis, a hierarchical approach using the stuck-at fault model at the first level and the arbitrary failure model at the second level, is used.The diagnosis algorithm reasons from first principles using constraint suspension.