Reliable VLSI sequential controllers
Sterling R. Whitaker, G.K. Maki, Manjunath Shamanna · International Journal of Electronics · 1991
A VLSI architecture for synchronous sequential controllers is resented that has attractive qualities for roducing reliable circuits. In these circuits, one hardware implementation can realize any flow table with a maximum of 2n internal states and m inputs. A real time fault detection means is resented along with a strategy for verifying the correctness of the checking hardware. This self-check feature can be employed with no increase in hardware. The architecture can be modified to achieve fail-safe designs. With no increase in hardware, an adaptable circuit can be realized that allows replacement of faulty transitions with fault-free transitions