Fault simulation and random test generation for speed-independent circuits
Feng Shi, Yiorgos Makris · 2004
We develop a fault simulator for input stuck-at faults in Speed-Independent circuits by extending Eichelberger's method. In order to achieve higher accuracy, a 13-valued algebra is adopted, the relative order of causal signal transitions is maintained, and time frames are unfolded in a careful manner. Based on this simulator, we propose a random test generation algorithm which reduces the probability that the circuit finds itself in non-deterministic states and helps it recover when this happens. Experimental results show that the combination of the two techniques achieves an average improvement of 18% in fault coverage.