A dynamically reconfigurable bluetooth base band unit
John Esquiagola, G. Ozari, M.Y. Teruya, Marius Strum, Wang Jiang Chau · 2005
In this paper, we present two different implementations of a dynamically reconfigurable Bluetooth Baseband Unit (BB/spl I.bar/Unit) using Xilinx Virtex-II FPGAs. The design flow started from a non-RTL SystemC model that has been functionally verified against an untimed SystemC golden model developed at Synopsys. This model was progressively refined (using Synopsys tools) until a synthesizable RTL model was obtained. The Xilinx modular design methodology was used to derive the partial and total bitstreams. Two partitions of the BB/spl I.bar/Unit were tested: header-payload (P1) and RX-TX (P2). The best results were obtained for the P2 partition on a XC2V250 component. Such a partition requires three sequential time intervals to process a Bluetooth packet: t/spl I.bar/rec + 1/spl I.bar/ini + t/spl I.bar/proc. The reconfigurable area occupied 4 columns and 24 bus-macros requiring a reconfiguration time of t/spl I.bar/rec=480 /spl mu/s, much smaller than the time slot of 625 is specified to either transmit or receive a packet.