A Low-Power H.263 Video CoDec Core Dedicated to Mobile Computing
Morgan Hirosuke Miki, Gen Fujita, Takeshi Kobayashi, Takao Onoye, Isao Shirakawa · 1997
A number of novel VLSI architectures are devised for an H.263 video codec core in terms of low bitrate visual communication. The potential of the practicability for mobile computing has been extremely explored by attempting not only to minimize the total chip area but also to reduce the power consumption to such an extent that the operation frequency can be slowed down to 15MHz. The whole encoding and decoding facilities have been integrated in the die area of 7.66 mm 2 by means of a 0.35m CMOS technology, with the dissipation of 146.60 mW from a single 3.3V supply.