A 150-mhz 4-bank 64m-bit Sdram With Address Incrementing Pipeline Scheme
Y. Kodama, M. Yanagisawa, K. Shigenobu, Takachika Suzuki, H. Mochizuki, Taiji Ema · 2005
We developed a 150-MHz 64M-bit SDRAM with an address incrementing pipeline scheme. For a synchronous read/write operation, we divided the column access path into three pipeline stages [l]. To increase the operating speed, we developed an address incrementing pipeline scheme, which can concurrently access data at two consecutive addresses. Using this scheme, the area penalty is 1.5% more than that of the conventional DRAM. For high frequency signals, we used T