Atlas: a dynamically parallelizing chip-multiprocessor for gigascale integration
Lucian Codrescu, D. Scott Wills, JAMES D. MEINDL · 2000
Single-chip multiprocessors are an important research direction for future microprocessors. The stigma of this approach is that many important applications cannot be automatically parallelized. This chapter presents a single-chip multiprocessor that engages aggressive speculation techniques to enable dynamic parallelization of irregular, sequential binaries. Thread speculation (multiscalar execution) and data value prediction are combined to enable the processor to execute dependent threads in parallel. The architecture performs a novel form of dynamic thread partitioning and includes an aggressive correlated value predictor. Several new microarchitectural structures manage inter-thread dependencies. On an eight processor system, simulated execution of SPECint95 binaries delivers a speedup of 3.4 over uniprocessor performance. This improvement is due entirely to the exploitation of dynamically extracted thread level parallelism. Introduction As semiconductor technology pushes towards billions of fast transistors on a chip, interconnect delay and design complexity become critical issues [56][23][84]. The processor architectures popular today exploit Instruction Level Parallelism (ILP). The fundamental ILP techniques in use today were developed in an era when transistor size