Fast High-Accuracy Binary Parallel Addition
Herbert C. Hendrickson · IEEE Transactions on Electronic Computers · 1960
Future designs of parallel digital computers will be concerned with increased accuracy in arithmetic operations. When the number of bits per operand is increased, one basic speed limitation to these operations is the time required to propagate carries in addition or borrows in subtraction. A quantitative method of evaluating the drastic reduction in time achieved by asynchronous addition techniques is described.