A 690 ps read-access latency register file for a GHz integer microprocessor
O. Takahashi, Joel A. Silberman, S.H. Dhong, H. Peter Hofstee, Nozomi Aoki · 2002
This paper describes a 690 ps read-access latency, 32 entry by 64 bit, 3 read-port, 2 write-port, register file with internal bypass. The register file has been fabricated as a pan of 1.0 GHz single-issue 64-bit PowerPC integer processor. Fabrication technology was IBM CMOS6X: 0.25-/spl mu/m drawn channel length, six-metal-layer (Al), 1.8 V nom. V/sub DD/. Self-resetting custom dynamic circuits are used exclusively. Read operation is accomplished by sensing the differential voltage of dual rail bit-lines. Read operation is followed by write operation in the same cycle. Whenever a read address is identical to a write address, the write data is forwarded by an output multiplexer. The register file has been tested and cycle by cycle operation in the processor environment verified at frequencies up to 1.0 GHz (1.8 V, 25/spl deg/C).