Programmable memory BIST and a new synthesis framework
Kamran Zarrineh, Shambhu Upadhyaya · 2003
The development of two programmable memory BIST architectures is first reported. A memory synthesis framework which can automatically generate, verify and insert programmable as well as non-programmable BIST units is developed as a vehicle to efficiently integrate BIST architectures in today's memory-intensive systems. Custom memory test algorithms could be loaded in the developed programmable BIST unit and therefore any type of memory test algorithm could be realized. The flexibility and efficiency of the framework are demonstrated by showing that these memory BIST units could be generated, functionally verified and inserted in a short time.