Multiple-Valued Constant-Power Adder for Cryptographic Processors
Yuichi Baba, Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki · 2009
This paper presents the design of a multiple-valued adder for tamper-resistant cryptographic processors. The proposed adder is implemented in multiple-valued current-mode logic (MV-CML). The important feature of MV-CML is that the power consumption can be constant regardless of the input values, which makes it possible to prevent power analysis attacks using dependencies between power consumption and intermediate values or operations of the executed cryptographic algorithms. In this paper, we present a multiple-valued constant-power adder based on the binary positive-digit (PD) number system and its application to RSA processors. The power characteristic of the proposed adder is evaluated with HSPICE simulation using 90 nm process technology. The proposed design can achieve constant power consumption with low performance overhead in comparison with the conventional binary design.