A 70-MHz 32-b microprocessor with 1.0- mu m BiCMOS macrocell library
Takashi Hotta, Tadaaki Bandoh, Atsuo Hotta, Takehito Nakano, S. Iwamoto, S. Adachi · IEEE Journal of Solid-State Circuits · 1990
A custom 529 K-transistor microprocessor with a five-stage pipeline has been implemented on a 12.98-mm/sup 2/ die. Employing BiCMOS macrocells, a 32-b execution unit, extensible ROM, RAM, a PLL (phase-locked loop) clock generator with bipolar drivers, and sense circuits, and a peak performance of 70 MIPS (million instructions per second) are achieved. Power consumption is 2.1 W at 40 MHz.>