Lightweight Multi-threaded Network Processor Core in FPGA
Piotr Buciak, Jakub Botwicz · 2007
The aim of this paper is to present a simple, lightweight, multi-threaded network processor core implemented in a FPGA circuit1. The authors prove that it is possible to design a processor core with hardware switched threads in a FPGA integrated circuit efficiently. The details of the processor core's architecture are described. The compilation results prove, that the proposed core is able to run at a frequency of 180 MHz in a high-end FPGA device.