Design of efficient radix-8 butterfly PEs for VLSI
T. Widhe, J. Melander, Lars Wanhammar · 2002
In this paper we discuss various aspects of VLSI implementation of radix-8 Sande-Tukey butterfly PEs. The Sande-Tukey algorithm is investigated to find regularities and simplifications. We argue that a bit-serial implementation of the butterfly PEs will be advantageous from an area point of view under most circumstances. The ideas are supported by a design example, a radix-8 butterfly PE that will be used in a 512 point FFT/IFFT processor aimed at OFDM applications.