A DFT Technique to Improve ATPG Efficiency for Sequential Circuits
Y. Bertrand, Frédéric Bancel, M. Renovell · 2005
The majority of DFT methods for sequential circuits are basedon scan designs (complete orpartial). One of the main drawbacksof these methods is the excessive test duration due to the long scan regism In this paper we present a new DFT concept for sequential circuits with the aim of improving testability with a reduced test duration to compare with scan methods. This method is based on cycle breaking and sequential depth reducing in test mode. These modijications imply observability and controllability problems which are solved by creating overlapping sub-circuits. The resulting sub-circuits are generated in such a way that they present a greatly reduced number of cycles and sequential depth. This strongly facilitates the task ofthe sequential test generalor: