Design of a single chip block coder for the EBCOT engine in JPEG2000
Amit Kumar Gupta, Michael L. Dyer, Lionel Hirsch, Saeid Nooshabadi, David Taubman · 2005
The main challenge in the VLSI design of an efficient JPEG2000 hardware is the block coder (BC) engine for the embedded block coding with optimised truncation (EBCOT). In this paper, we present the VLSI design of a BC system that can process 21 mega pixels per second. For the bit plane coder (BPC), we employ a concurrent symbol processing (CSP) algorithm to process of all 4 sample locations within a stripe-column in a single clock cycle during a pass. The BPC produces on average, 1.21 context data (CxD) pairs per clock cycle. In addition, we have designed an arithmetic coder (AC) that processes 2 CxDs/clock cycle. To allow for an efficient coupling of the proposed BPC and AC modules, we also propose a novel architecture for an intermediate buffer. The BC chip implemented on TSMC 0.18 /spl mu/m technology, occupies an area of 1.6 mm/sup 2/, with an equivalent gate count of 95,000, that includes 24576 memory bits. It runs at a clock frequency of 100 MHz. Its high processing throughput is the highest ever reported for a JPEG2000 BC engine capable of handling both normal and causal modes of operation.