A 1GHz Direct Digital Frequency Synthesizer Based on the Quasi-Linear Interpolation Method
Ashkan Ashrafi, Aleksandar Milenković, Reza R. Adhami · 2007
The paper presents a novel architecture for a direct digital frequency synthesizer (DDFS) based on the Quasi-Linear interpolation (QLIP) method. The four-segment QLIP is utilized to realize a DDFS with a spurious free dynamic range (SFDR) of 63.2dBc. The DDFS chip featuring a 5-stage pipeline is implemented in TSMC 0.13μm technology. The chip occupies 9874μm2, consumes 8.2μW/MHz, and runs at 1GHz clock rate.