Test generation for I/sub DDQ/ testing and leakage fault detection in CMOS circuits
U. Mahlstedt, Matthias Heinitz, J. Alt · European Design Automation Conference · 1992
The authors describe a two-stage method to generate test sets for quiescent power supply current, I/sub DDQ/, testing and to determine the leakage fault coverage for given test pattern sets. The method is integrated within a fault simulator. It is proved that any complete test pattern set generated for stuck-at faults detects all leakage faults caused by intra-gate shorts within a static CMOS circuit if the circuit contains only primitive gates (inverter, buffer, AND, NAND, OR, NOR). >