SPARC implementations: ASIC vs. custom design
Masood Namjoo · 2003
The first two implementations of the SPARC architecture, MB86900 and CY7601, were designed using high-speed CMOS technology with processor clock speed in the range of 16.6 to 33 MHz. In a system with a reasonable size external cache, these processors execute integer operations at a rate of approximately 1.5 clock cycles per instruction, resulting in a sustained performance in the range of 10 to 20 MIPS (millions of instructions per second). MB86900 design uses a single 20000-gate 1.3- mu m CMOS gate array and operates at a cycle time of 60 ns. CY7601 is a full custom chip designed using a 0.8- mu m CMOS process and operates at a cycle time of 30 ns. The basic features of these processors, their similarities and differences, and the tradeoffs used in their design. Design verification, test generation, and fault simulation are addressed.>