Programmable VLSI systolic processors for neural network and matrix computations
Paolo Ienne Lopez · Infoscience (Ecole Polytechnique Fédérale de Lausanne) · 1996
These Ecole polytechnique federale de Lausanne EPFL, n° 1525 (1996)Laboratoire d'architecture de processeurs Reference doi:10.5075/epfl-thesis-1525Print copy in library catalog Record created on 2005-03-16, modified on 2017-05-12