A Memory-Efficient Pattern Matching with Hardware-Based Bit-Split String Matchers for Deep Packet Inspection
Hyun Jin Kim, Hong‐Sik Kim, Jung-Hee LEE, Jin-Ho Ahn, Sungho Kang · IEICE Transactions on Communications · 2010
This paper proposes a hardware-based parallel pattern matching engine using a memory-based bit-split string matcher architecture. The proposed bit-split string matcher separates the transition table from the state table, so that state transitions towards the initial state are not stored. Therefore, total memory requirements can be minimized.