Hardware Friendly Vector Quantization Algorithm
Shigeki Matsubara, Hiroomi Hikawa · 2005
This paper proposes a new vector quantization algorithm that can be directly implemented by hardware and its performance is discussed. The algorithm is based on the assumption that most of the vector elements in the same class fall within a certain range. The proposed algorithm provides very fast vector quantization with a dedicated hardware. VHDL simulations with real world data verify the feasibility of the system followed by the circuit size and speed evaluation. Results show that the proposed system has higher performance than those of K-nearest-neighbor method or neural network approach.