A parallel pattern mixed-level fault simulator
Tyh-Song Hwang, Chung Len Lee, Wen Zen Shen, Ching Ping Wu · 1990
This paper describes a parallel pattern mixed level, i.e. switch-level and gate-level, fault simulator. The switch-level allows the simulator to treat faults at the transistor level while the gate level simulation conserves the simulation speed and the parallel pattern strategy further enhances the simulation speed for more than one order of magnitude.