Pipelined microprogrammed control of a real-time signal processor
David Lynch, L. W. Tower · 1973
The design of a pipelined microprogrammed controller for a real-time signal processor is described. The signal processor has an arithmetic functional unit with four multipliers and four adders, eight general-purpose registers, 16 index registers, a program memory, and a number of data memories. To realize the full potential of the four multiplers, it is necessary to overlap operations such as instruction fetch, operand fetch, instruction execution, and result store. This overlap requirement and the desire for a flexible instruction set led to the development of a pipelined microprogrammed controller. The controller operates by decoding encoded instructions at each stage in the instruction pipe. Decoded microprogram instructions can modify encoded instructions as they propagate down the instruction pipe. To decrease the width of both machine instructions and micro-instructions, the control function is shared by a small number of global control registers.