Augmenting DR-ASIP flexibility through multi-mode custom instructions
Antoine Trouvé, Kazuaki J. Murakami · ACM SIGARCH Computer Architecture News · 2011
This paper introduces a simple method called multimode custom instructions, which aims at reducing the power consumption of the register file of tightly coupled dynamically reconfigurable application specific instruction set processors (DR-ASIPs). To this end, it proposes to divide custom instructions into two sets depending on criteria related to their size, distribution and reuse rate. Performance is measured on a RISC DR-ASIP with a subset of MiBench using an original automatic custom instruction generator from assembly based on the dancing link algorithm. The results show that this method makes it possible to drop the accesses to the register file made by CIs by up to 47 % with no performance hit, and to reduce the use of the context memory by up to 40 % compared to a reference architecture.