Systolic circuits for fast transform algorithms
M. Marchesi, G. Orlandi, Francesco Piazza · 2003
Fast algorithms for calculating the discrete Hartley transform and the Fermat number transform (FNT) are discussed from an architectural point of view. Several systolic architectures for the real-time computation of these transforms are presented. In particular, the cascade architecture for computing the FNT with the decimation-in-time algorithm is presented.>